1. Field of the Invention
The present invention relates to digital image processing circuits, and in particular to a circuit enabling modification of the coding of the colors associated with the pixels of a digital image.
2. Discussion of the Related Art
A digital image is conventionally formed of pixel rows and columns. Each image pixel is especially associated with a color. A common type of coding is the so-called RGB coding, in which the colors are represented by three components: red (R), green (G), and blue (B), each of which is conventionally coded over a same number of bits. In such a coding, the number of bits used for the R, G, B components determines the number of possible colors for each image pixel. For example, R, G, and B components coded over 8 bits enable describing 23xc3x978, that is, more than 16 million different colors. It should be noted that all the pixels of a same image are conventionally coded with a same number of bits. A component A corresponding to a transparency information is sometimes added to the three R, G, and B components.
In certain applications, it may be desired to reduce the number of bits used to code the colors of the pixels of a digital image. Indeed, the more the colors of the pixels of an image are coded over a large number of bits, the more this image represents a great amount of information. Reducing the number of color coding bits enables reducing the amount of information represented by an image, which enables storing the image in a reduced memory space, processing it faster, or transmitting it, for example with a modem, in a shorter time.
A known solution to reduce the number of bits coding an image consists of creating a color look-up table (CLUT) containing a restricted number of colors coded like the original colors of the image pixels. The RGB coding of the original color of each pixel is then replaced with a CLUT code corresponding to an address of a color of the color look-up table, which is the closest to the original pixel color. The number of colors in the look-up table being reduced, the coding of its addresses may include a reduced number of bits as compared to that used in the RGB coding of the original colors. Thus, the CLUT code of a color can have a reduced number of bits with respect to the number of bits of an RGB code. For example, an address coded over eight bits enables completely addressing a look-up table of 28 =256 colors. Considering the preceding example, and having a look-up table of 256 colors, each of which is RGB-coded over 24 bits, the 24-bit RGB code of the original color of each pixel can be replaced with an 8-bit color look-up table address. Such a substitution enables substantially reducing (approximately by three in this example) the amount of information represented by an image.
In a digital image processing device, previously described complete (RGB type) and reduced (CLUT type) color codings are used. For example, an image may be created with a complete color coding, then be transformed to have a reduced color coding, which enables transmitting it rapidly by modem or retouching it by means of a software. Finally, such an image may be transformed back to recover a complete color coding, which for example enables displaying it on a computer screen. Some digital image processing devices are intended for receiving several images and assembling them in a single image. As an example, a blitter circuit, conventionally used to create an image based on several images of various origins, will be considered hereafter.
FIG. 1 schematically shows, in the form of blocks, an example of an image processing device 2, for example a computer graphics board. Device 2 includes a memory 4 in which are stored several digital images that can have different complete or reduced color codings. Memory 4 (MEM) is connected to a bus 6 to receive write and read control signals and to provide or receive data. A central processing unit (CPU) 8 is connected to bus 6 to receive or provide data or control signals. Device 2 also includes a blitter 9 provided with a calculation circuit 10 (BLITTER CORE) and with two intermediary or buffer memories (BUF1) 12 and (BUF2) 14. Circuit 10 includes a first and a second image inputs respectively connected through intermediary memories 12 and 14 to receive data from bus 6. Circuit 10 includes a data output that forms the output of blitter 9. This output is connected through an intermediary memory or buffer (BUF3) 16 to a display device (DISP) 18. Intermediary memory 16 is also connected to bus 6 to receive control signals or data from the central processing unit and provide data thereto.
Conventionally, blitter core 10 of blitter 9 is provided to process images having a given color coding, for example a CLUT coding. Images having a different color coding, in this example, an RGB coding or the like, must be converted to have the CLUT coding before they can be provided to blitter core 10. Thus, images having a color coding that is not readily usable by the blitter core are read from memory 4 by central processing unit 8 that converts their coding, then controls their writing into one of intermediary memories 12 or 14 of blitter 9. When both intermediary memories 12 and 14 contain images having a color coding usable by blitter core 10, circuit 10 reads their respective contents and generates an image that it provides to intermediary memory 16. It should be noted that the images generated by circuit 10 may be in a code that is not readily usable by display device 18. In such a case, the image contained in intermediary memory 16 will have to be read and its color coding will have to be converted by processor 8 before it can be provided to display device 18 via intermediary memory 16.
In such an operation, the central processing unit must frequently be used to convert images to the format accepted by the blitter core. Such a use of the CPU does not enable using it for other tasks, which adversely affects the performance of the system in which circuit 10 is integrated, for example a microcomputer.
The only solution to increase the system performance consists of using a faster CPU, but such a solution is expensive.
The present invention aims at overcoming the disadvantages of known blitters.
An embodiment of the present invention provides a digital image processing circuit enabling saving CPU processing time of the system in which it is integrated.
The image processing circuit includes a circuit having a color coding conversion function and an image composition function.
The image processing circuit provides a particularly low-cost solution.
The image processing circuit is adapted to replace an input code associated with a pixel of the image with an output code selected in first storage means containing a set of codes, which includes an input bus adapted to receive the input code, an output bus adapted to provide the output code, said first storage means, means of address calculation of the first storage means, means of address selection of the first storage means between the input code and an address code generated by the address calculation means, second storage means adapted to contain an address code generated by the address calculation means, and means of selection of the output code between a code read at the current address of the first storage means and said code contained in the second storage means.
According to an embodiment of the present invention, the address calculation means include an address generator adapted to provide predetermined address codes to the addressing means, and a data comparison circuit provided to compare the first code with the codes stored at the predetermined addresses in the first storage means, to determine which of the compared codes is closest to the first code, and to control the second storage means to store the code of the address at which the closest compared code is stored in the first storage means.
According to an embodiment of the present invention, the input and output buses each include first, second, third, and fourth sub-buses each having a same number of bits, the address selection means include first, second, third, and fourth multiplexers, the first inputs of which are respectively connected to the first, second, third, and fourth input sub-buses, the output of the first multiplexer being connected to the second inputs of the second, third, and fourth multiplexers, the first storage means include a first, a second, a third, and a fourth identical memory circuits, the addressing inputs of which are respectively connected to the outputs of the first, second, third, and fourth multiplexers, and the output code selection means include a fifth multiplexer, the first input of which is connected to the data output of the first memory circuit and the output of which is connected to the first output sub-bus, the second, third, and fourth sub-buses being respectively connected to the data outputs of the second, third, and fourth memory circuits.
According to an embodiment of the present invention, the address generator is formed with a counter adapted to providing a predetermined series of address codes to the second input of the first multiplexer, and the data comparison circuit includes: a calculator connected for respectively receiving the codes provided to the first three input sub-buses and the codes provided by the first three memory circuits, and provided to provide a digital signal equal to the difference between these codes, and a memory comparator connected for keeping the smallest difference digital signal calculated for the predetermined series of address codes and for controlling the second storage means to store the code of the address at which the codes corresponding to the smallest difference are stored in the first storage means.
The present invention also provides a method of image processing by means of a digital image processing circuit according to one of the preceding embodiments, which consists of receiving images, the color codes of which each correspond to an address in a color reference table, and replacing each address with the color code designated by this address in the reference table.
According to an embodiment of the present invention, the method includes receiving images, the colors of which are coded in a predetermined way, and of replacing the code of each color of the image with an address in a color reference table.
According to an embodiment of the present invention, the method includes the steps of storing, in the first, second, third, and fourth memory circuits, respective red, green, and blue color and transparency codes, providing a respective red, green, and blue color and transparency code to the first, second, third, and fourth input sub-buses, and controlling the multiplexers of the address selection means and of the output selection means to provide the first, second, third, and fourth memory circuits with the codes received on the first, second, third, and fourth input sub-buses, and to provide the four output sub-buses with the respective codes provided by the four memory circuits.
According to an embodiment of the present invention, the method includes the steps of storing, in the first, second, third, and fourth memory circuits, respective red, green, and blue color and transparency codes, providing an address code to the first input sub-bus, and controlling the multiplexers of the address selection means and of the output selections means to provide the first, second, third, and fourth memory circuits with the code received on the first input sub-bus, and to provide the four output sub-buses with the respective codes provided by the four memory circuits.
According to an embodiment of the present invention, the method includes the steps of storing in the first, second, third, and fourth memory circuits respective red, green, and blue color and transparency codes, providing an address code to the first input sub-bus, providing a transparency code to the fourth input sub-bus, and controlling the multiplexers of the address selection means and of the output selection means to provide the first, second, and third memory circuits with the code received on the first input sub-bus, to provide the fourth memory circuit with the code received on the fourth input sub-bus, and to provide the four output sub-buses with the respective codes provided by the four memory circuits.
According to an embodiment of the present invention, the method includes the steps of storing in the first, second, third, and fourth memory circuits respective red, green, and blue color and transparency codes, providing the first, second, and third input sub-buses with respective red, green, and blue color codes, activating the counter, and controlling the multiplexers of the address selection means and of the output selection means to provide the first three memory circuits with the address codes provided by the counter, and to provide the first output sub-bus with the address code provided by the second storage means.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.